Verification and Validation/Debug Methodologies

WG Chair: Dimitris Gizopoulos (University of Athens – Greece)
WG Vice Chair: Maria K Michael (University of Cyprus – Cyprus)

The objectives of Work Group 3 are:

1. Methodologies and metrics for dependability analysis
   Apparently, development of effective approaches for dependability/reliability enhancement, first requires the identification of major dependability threats, their characterization and analysis. This activity of the COST Action focuses on methodologies and metrics/measurements for dependability analysis of multicore systems. In particular, classic metrics such as reliability, availability, maintainability, will be analyzed in the context of massively parallel (and possibly highly redundant) multicore systems.
2. Formal verification
   The need for formal verification techniques grows with the complexity of the systems to be designed. Formal verification can prove the functional correctness of systems such as: cryptographic protocols, combinational circuits, digital circuits with internal memory, and software. The formal verification methods must be revisited to also formally prove that a system is able to tolerate the occurrence of a fault.
3. Reliability analysis, modeling and evaluation of multicore systems
   Estimation of the effectiveness of the different techniques, from physical/circuit/logic levels to software/hardware ones, requires the development of suitable models able to evaluate the achievable reliability by using a mixture of the available techniques. Modelling should start from the effects of the possible faults, in particular of their occurrence probabilities. From these models a statistical estimation of the reliability and availability of the multicore systems will be carried out.
4. Validation/debug at post-production level
   Comprehensive design verification at pre-silicon stage is severely limited by the huge complexity of massively parallel architectures and tremendous pressure for short time-to-market. It is widely accepted that post-silicon design validation and debug is an absolutely necessary step to guarantee that design bugs do not escape. Infamous design bugs that intruded in leading-edge microprocessors in the last decade prove the need for this step. Post-silicon validation/debug is a process that is closely connected with system dependability/reliability; this activity of the COST Action will focus on post-production (prototypes) validation and its relation with fault tolerance.