System level design, on-line testing/fault tolerance

WG Chair: Cristiana Bolchini (Politecnico di Milano – Italy)
WG Vice Chair: Salvatore Pontarelli (University of Rome “Tor Vergata” – Italy)

The objectives of Work Group 2 are:

1. Software and protocols for Fault tolerance
   Temporary and permanent faults can cause misbehaviours during the execution of the application in multicore processors. A fault tolerant strategy requires a) the identification of the occurrence of a fault (fault detection), b) the limitation of the effect of the fault (fault confinement), and c) the masking of the fault effects (fault masking). These subsequent actions can be performed by suitable software procedures that can be developed at the OS or the application level. Similarly, communication protocols that specify the set of rules that the communication should respect, the set of actions forming the fault tolerant methodologies can be defined as a protocol for reliable computations.
2. Architectural solutions for Fault tolerance in multicore processors
   The digital design of complex systems at nanoscale requires also predisposing a set of architectural solutions to detect, mitigate and take the suitable countermeasures, with respect to a wide range of faults that can occur. Natural redundancy of multicore architectures gives the chance of implementing high-level modular redundancy-based techniques. These techniques will require modification to the interconnection between the different cores, suitable access mechanism to the shared parts (e.g. memories) and so on.