Methodologies and techniques for manufacturing reliable nanoscale devices

WG Chair: Lorena Anghel (Grenoble INP, TIMA Laboratory – France)
WG Vice Chair: Mehdi Tahoori (Karlsruhe Institute of Technology – Germany)

The objectives of Work Group 1 are:

1. Defect and Fault Modelling in nanoscale devices
   Technology scaling of silicon technologies as well as new emergent ones cause more and more transient and permanent failures of devices, and interconnects. Several examples are the following ones: single-event upsets (soft errors) that impact field-level product reliability, accelerated lifetime testing (burn-in) that becomes unfeasible as supply voltages decrease, atomic-scale effects such as non-catastrophic gate oxide breakdown or highly resistive vias, or new defects appearing in innovative technologies.
2. Evaluation and Mitigation of Variation effects on nanoscale technologies
   Silicon and emerging technologies need accurate consideration of process variations and resulting parametric uncertainty in logic and circuit design. Manufacturing process variations dramatically reduce reliability and yield of fabricated chips. Therefore, it is mandatory to insert in the early stages of the design strategies to make the final circuit highly adaptive against faults induced by process variation problems, for instance by means of automatic introduction of asynchronous circuits. Specific effort can be devoted also at layout level to minimize the impact of process variation on the final design. These techniques have the advantage of being quite insensitive to latency and viable to low power design, offering at the same time a good level of reliability and security.
3. Defect tolerant manufacturing of nanoscale CMOS and innovative technology (QCA, crossbar, etc.)
   In the effort of reducing size together with the huge cost of manufacturing, design, verification and test, there is a general acceptance of the fact that the requirement of achieving “100% correctness” for devices and interconnects cannot be fulfilled anymore. Furthermore, as systems become too complex, automatic insertion of robustness into the design will become a priority. Potential solutions include automatic introduction of specific redundant techniques at Logic/Circuit/Physical design levels, on-chip reconfigurability for fault tolerance, development of adaptive and self-correcting or self-healing circuits, MTTF-aware design, BISR, soft-error correction techniques to deal with yield and reliability and software-based fault- tolerance.
4. Electronic Design Automation methodologies and tools for design and test of nanoscale CMOS and alternative technologies
   Automation process is mandatory for mitigation techniques insertion as well as for evaluation of such complex circuits.