medianproject logo

COST Action IC1103

cost action logo

Foreword
Lorena Anghel, Olivier Heron, MEDIAN’15 Program Chairs
Elena Gramatova, Maksim Jenihhin, MEDIAN’15 General Chairs


Keynote: Reliability Challenges for Cyber-Physical Systems
Zebo Peng, Linköping University, SE


Paper session I: Fault Tolerance and Test Techniques for Low Power Design

BTI Analysis for High Performance and Low power SRAM Sense Amplifier Designs
Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui – Delft UT, NL; Halil Kukner, Pieter Weckx, Praveen Raghavan, Francky Catthoor – IMEC, BE

Power-Aware Online Detection of Hardware Defects for Manycore Systems with DVFS Support
Mohammad-Hashem Haghbayan, Amir-Mohammad Rahmani, Mohammad Fattah, Pasi Liljeberg, Juha Plosila and Hannu Tenhunen – Univ. Turku, FI

Poster session

A new adaptive system for software-based test generation of processors
Jan Hudec and Elena Gramatova – Slovak UT, SK

Radiation Impact on Mechanical Application Driven by FPGA-based Controller
Jakub Podivínský, Marcela Simkova and Zdenek Kotasek – Brno UT, CZ

A Fault Resilient Routing Algorithm for Heterogeneous 3D NoCs
Masoumeh Ebrahimi (1,2), Ronak Salamat (3), Nader Bagherzadeh (3), Masoud Daneshtalab (1,2), 1 – Univ. Turku, FI; 2 – KTH, SE; 3 – Univ. California, US

Mixed Criticality Metric for Safety-Critical Cyber-Physical Systems on Multi-Core Architectures
Viacheslav Izosimov – KTH, SE, Semcon Sweden AB, SE; Erik Levholt – Svenska Grindmatriser AB, SE

Secured Connectivity of Distributed Agents in Presence of Many NoC Faults
Mohammad Fattah, Pasi Liljeberg and Juha Plosila, Univ. Turku, FI

On Aging of Latches’ Robustness
Martin Omana, Luz Antuanet Adanaque Infante, Cecilia Metra – Univ. Bologna, IT; Daniele Rossi – Univ. Southampton, UK

Influence of Reconfiguration Techniques for Dynamically Scheduled Superscalar Processors on Power Consumption
Tobias Koal, Robert Karas, Heinrich Theodor Vierhaus – Brandenburg UT, DE; Mario Schölzel – IHP and Univ. Potsdam, DE

Extended Checkers for Control Part of Routers in Network-on-Chips
Ranganathan Hariharan, Behrad Niazmand, Thomas Hollstein, Jaan Raik and Gert Jervan – Tallinn UT, EE

Simulation framework for optimizing SRAM power consumption under reliability constraint
Florian Cacho – STMicroelectronics, FR; Erwan Piriou, Olivier Heron – CEA, LIST, FR; Vincent Huard – STMicroelectronics, FR

Paper session II: Verification and Test Techniques for Reliable Design

Evaluation of Failures Masking Across the Software Stack
Thiago Santini, Paolo Rech, Anderson Sartor, Ulisses B. Corrêa, Luigi Carro and Flavio R. Wagner – UFRGS, BR

A novel Formal Verification Framework for future MPSoC Architectures
Christian Schöler, René Krenz-Baath – Hochschule Hamm-Lippstadt, DE; Roman Obermaisser, – Univ. Siegen, DE


Invited talk: Technology Scaling and Reliability Challenges in the Multicore Era
Vincent Huard, STMicroelectronics, FR


Paper session III: Dependable Systems and Components

Efficient online testing of an array of reconfigurable RISC Processors
S. Pagliarini S. Pontarelli, J. Mathew, D.K. Pradhan – Univ. of Bristol, UK; I. Sourdis, D.A. Khan, A. Malek, S. Tzilis – Chalmers UT, SE; G. Smaragdos, C. Strydis – Erasmus Medical Center, NL

Measuring and Identifying Aging-Critical Paths in FPGAs
Petr Pfeifer – TU Liberec, CZ; Jaan Raik, Maksim Jenihhin, Raimund Ubar – Tallinn UT, EE; Zdenek Pliva – TU Liberec, CZ

Dynamic Voltage Scaling with Fault-Tolerance for Lifetime Operation
Jorge Semião – Univ. Algarve, PT; Carlos Leong – INESC-ID, PT; Ruben Cabral, Marcelino Santos, Isabel Teixeira and Paulo Teixeira – IST / INESC-ID, PT

Paper session IV: Dependable Multicore Systems and Processors Testing and Self-repair

Software-Based Self-Repair for Heterogenous Multi-Core Systems
Sebastian Müller, Heinrich Theodor Vierhaus – Brandenburg UT, DE; Mario Schölzel – IHP and Univ. Potsdam, DE

Universal Pseudo-random Generation of Assembler Codes for Processors
Ondrej Cekan, Marcela Simkova and Zdenek Kotasek – Univ. Brno, CZ

Exploring check-pointing and rollback recovery under selective SBST in Chip Multi-Processors
Michael Skitsas, Chrysostomos Nicopoulos and Maria Michael – Univ. Cyprus, CY

 
 

COST is supported by the EU Framework Programme Horizon 2020