Message from the Organizers
Maria K. Michael, Ozcan Ozturk, MEDIAN’14 Program Chairs
Oliver Bringmann, Mehdi Tahoori, MEDIAN’14 General Chairs
Message from the COST Action Chair
Marco Ottavi
Multi-Core Emulation for Dependable and Adaptive Systems Prototyping
C. Bolchini and M. Carminati
Fault-tolerant Routing Approach for 3D Stacked Meshes
M. Ebrahimi, M. Daneshtalab and J. Plosila
BTI reliability from Planar to FinFET nodes: Will the next node be more or
less reliable?
H. Kukner, P. Weckx, P. Raghavan, B. Kaczer, D. Jang, F. Catthoor, L. Van der Perre, R. Lauwereins and G. Groeseneken
Analysis of Random Dopant Fluctuations and Oxide Thickness on a 16nm L1
Cache Design
C. Eryilmaz, A. Seyedi, O. S. Unsal and A. Cristal
Generation of Equivalent Congurations for Defect Tolerance
and Yield Improvement of FPGAs
P. M. B. Rao, A. Amouri and M. B. Tahoori
A Complex Control System for Testing Fault-Tolerance Methodologies
J. Podivinsky, M. Šimková and Z. Kotásek
Improving the Reliability of Skewed Caches through ECC based Hashes
S. Yegin, B. Karsli, O. Ergin, M. Ottavi, S. Pontarelli and P. Reviriego
A new Diagnostic method for VLIW Processors
D. Sabena, L. Sterpone and M. Sonza Reorda
Aging Monitoring Methodology for Built-In Self-Test Applications
J. Semião, J. Coelho, C. Leong, M. Santos, I. Teixeira and P. Teixeira
Posters
BADR: Boosting Reliability Through Dynamic Redundancy
I. Alouani, S. Niar, M. Saghir and F. Kurdahi
Automatic Detection and Correction of Defective Pixels for Medical and Space Imagers
E. Cohen, M. Shnitser, T. Avraham, O. Hadar and Y. Dotan
Implementing Double Error Correction Orthogonal Latin Squares Codes in Xilinx FPGAs
M. Demirci, P. Reviriego and J. A. Maestro
On Reliability Enhancement Using Adaptive Core Voltage Scaling and Variations on TSMC 28nm
LP process process FPGAs
P. Pfeifer and Z. Pliva
Power and Performance Optimization in Long-term Operation
J. Semião, A. Romão, C. Leong, M. Santos, I. Teixeira and P. Teixeira