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COST Action IC1103

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The First Workshop on Manufacturable and Dependable
Multicore Architectures at Nanoscale (MEDIAN'12)
Annecy, France, June 1st, 2012

Message from the Organizers
Said Hamidioui, Hans Manhaeve

Message from the COST Action Chair
Marco Ottavi

Power and Aging Characterization of Digital FIR Filters Architectures
by Andrea Calimera, Wei Liu, Enrico Macii, Alberto Nannarelli and Massimo Poncino

Analyzing Combined Impacts of Parameter Variations and BTI in Nano-scale Logical Gates
by Seyab Khan and Said Hamdioui

Hybrid CMOS/Magnetic Process Design Kit and application to the design of reliable and low-power non-volatile logic circuits
by Guillaume Prenat, Bernard Dieny, Gregory Di Pendina and Kholdoun Torki

Towards the Design of Tunable Dependable Systems
by Cristiana Bolchini, Matteo Carminati and Antonio Miele

Neutrons-Induced Multiple Output Errors: a Reality on GPUs
by Paolo Rech, Caroline Aguiar, Christopher Frost and Luigi Carro

Soft Error Propagation and Correlation Estimation in Combinational Network
by Liang Chen and Mehdi Tahoori

Low Complexity Concurrent Error Detection for Complex Multiplication
by Pedro Reviriego, Christopher Bleakley and Juan Antonio Maestro

Using deterministic test vectors to test FPGA circuit
by Martin Rozkovec, Jirı Jenıcek and Zdenek Plıva

Embedding Fault-Tolerance with Dual-Level Agents in Many-Core Systems
by Liang Guang, Syed Asad, Tony Yang, Juha Plosila and Hannu Tenhunen

Reliability-Aware 3D Chip Multiprocessor Design
by Ismail Akturk and Ozcan Ozturk

Methodology for Increasing Reliability of FPGA Design via Partial Reconguration
by Jan Kastil, Martin Straka and Zdenek Kotasek

Monitoring Single Event Transient Effects in Dynamic Mode
by Varadan Savulimedu Veeravalli and Andreas Steininger

Verification of Fault-tolerant Methodologies for FPGA systems
by Marcela Simkova and Jan Kastil

On the Evaluation of the Performance Overhead of a Commercial Embedded Hypervisor
by Salvatore Campagna and Massimo Violante

On-Line Software-Based Self-Test for Data TLBs
by Georgios Theodorou, Nektarios Kranitis, Antonis Paschalis and Dimitris Gizopoulos

Toward Selective Software-Based Self-Testing in Future Multi-Core Microprocessors
by Michael A. Skitsas, Chrysostomos A. Nicopoulos and Maria K. Michael

 
 

COST is supported by the EU Framework Programme Horizon 2020