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COST Action IC1103

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Proceedings

Foreword, Maksim Jenihhin, Marco Ottavi, Andreas Steininger, Jaan Raik, Mario Schölzel, Thomas Hollstein

Keynote Erik Jan Marinissen, Principal Scientist at IMEC (Leuven, Belgium), Murphy Goes 3D

Poster Session & PhD Forum

Alberto Nannarelli, Reliability in Warehouse-Scale Computing: Why Low Latency Matters

Ondrej Cekan and Zdenek Kotasek, Software Fault Tolerance: the Generation Using Universal Approach

Martin Krčma, Zdenek Kotasek and Jan Kastil, Redundancy free fault tolerant FPNNs

Juraj Šubín and Štefan Krištofík, A new system for BIST architecture generation for embedded memories in SoCs

Jakub Podivínský and Zdenek Kotasek, The Use of FPGA-accelerated Functional Verification for Processor Fault Tolerance Evaluation

Mohammad-Hashem Haghbayan, Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila and Hannu Tenhunen, Dynamic Power Management and Test for Many-Core Platforms in the Dark Silicon Era

Stefan Scharoba and Heinrich T. Vierhaus, Automating the Evaluation of Design Choices for Dependable Integrated Circuits [+DEMO]

Sang Van Doan, Jiri Vavra, Zdenek Kolka and Dalibor Biolek, Threshold-Type, Memristive Emulators for Analog Computations and Signal Processing [+DEMO]

Session 1: Ageing and Reliability

Sergei Kostin, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Thiago Copetti and Fabian Vargas, Accurate NBTI-induced Gate Delay Modeling Based on Intensive SPICE Simulations

Yong Zhao and Hans Kerkhoff, Predicting Aging Caused Delay Degradation with Alternative IDDT Testing in a VLIW Processor

Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Praveen Raghavan, Francky Catthoor and Wim Dehaene, Comparative BTI Impact for SRAM Cell and Sense Amplifier Designs

Ruben Cabral, Jorge Semião, Marcelino Santos, Isabel Teixeira and Paulo Teixeira, Dynamic Voltage and Frequency Scaling for Long-Term and Fail-Safe Operation

Session 2: Modelling and Analysis

(Invited Talk) Raimund Ubar, Professor (Tallinn UT, Estonia), Decision Diagrams for Diagnostic Modelling

Petr Pfeifer, Towards Dependability and Security of Modern SoC Using AmBRAMs – An Advanced Set of Methods and Tools on Modern Nanoscale FPGAs

Milan Babic and Milos Krstic, GALS Methodology for Substrate Noise Reduction in BiCMOS Technologies

Varadan Savulimedu Veeravalli and Andreas Steininger, Can we trust SPICE-Level SET Models?

Session 3: Concurrent Error Detection & Correction

Hale Ogur, Gozde Boztepe, Davut Deniz Yavuz, Serhat Gesoglu, Aziz Eker, Gulay Yalcin, Osman Unsal and Oguz Ergin, Exploiting Existing Replicas of Stack Pointer in Register File for Error Detection

Emrah Islek, Serdar Zafer Can, Oguz Ergin and Abdulaziz Eker, Collective Pointing: Protecting Pointer Values Against Soft Errors

Pietro Saltarelli, Behrad Niazmand, Ranganathan Hariharan, Jaan Raik, Gert Jervan and Thomas Hollstein, A Framework for Area-Efficient Concurrent Online Checkers Design

Ioannis Voyiatzis, Online Testing of ROMs with Input Vector monitoring

 

Thematic Day of EU Projects

H2020 ICT RIA IMMORTALIntegrated Modelling, Fault Management, Verification and Reliable Design Environment for Cyber-Physical Systems” (Partners: Tallinn UT, DLR, TU Graz, U Twente, IBM, Testonica, Recore), Jaan Raik, Gerard Rauwerda, Yong Zhao and Konstantin Shibin

FP7 ICT CP CLERECO Cross-Layer Early Reliability Evaluation for the Computing cOntinuum” (Partners: POLITO, TU Catalonia, CNRS, Thales, U Athens, Yogitech, ABB, U Montpellier 2), Stefano Di Carlo

H2020 IA CPSE Labs CPS Engineering Labs – expediting and accelerating the realization of cyber-physical systems”, (Partners: Fortiss, KTH, ONERA, U Newcastle, Offis, Indra, Steinbeis, CNRS, ONERA, TU Madrid), Viacheslav Izosimov and Claire Ingram

FP7 ICT CP BASTIONBoard and SoC Test Instrumentation for Ageing and No-Failure-Found“, (Partners: Testonica, Infineon, HSHL, Tallinn UT, Aster, POLITO, U Twente, Lund U), Sergei Devadze and Maksim Jenihhin

FP7 JTI ARTEMIS EMC2Embedded Multi-Core Systems for Mixed Criticality Applications in Dynamic and Changeable Real-Time Environments”, (Partners: Infineon + 98 partners), Werner Weber

DCPS DAAD thematic network for collaborative studies “Dependable Cyber Physical Systems”, Heinrich T. Vierhaus

Focus on Horizon 2020

Invited Talk “H2020 Cooperation and Funding Opportunities”, Aavo Kaine, Estonian Research Council

Invited Talk “Secrets of Successful Project Application”, Silver Toomla, consultancy Invent Baltics

 

 
 

COST is supported by the EU Framework Programme Horizon 2020