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COST Action IC1103

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publications

In this page we list all the publications fostered by this COST Action.

2013

International Journals

  • P. Reviriego, S. Pontarelli, J. A. Maestro and M. Ottavi, "A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only," in IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 3, pp. 479-483, 2013. doi

International Proceedings

  • T. Drahonovsky, M. Rozkonev and O. Novak, "Relocation of reconfigurable modules on Xilinx FPGA," in Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp. 175-180, 2013. bibtex
    @inproceedings {ddecs2013a,
      title = {Relocation of reconfigurable modules on Xilinx FPGA},
      booktitle = {Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)},
      pages = {175-180},
      year = {2013},
      month = {April},
      yy = {2013},
      mm = {4},
      author = {T. Drahonovsky and M. Rozkonev and O. Novak} }
  • P. Pfeifer, Z.Pliva, M. Scholzel, T. Koal and H. Vierhaus, "On Performance Estimation of a Scalable VLIW Soft-Core in XILINX FPGAs," in Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp. 181-186, 2013. bibtex
    @inproceedings {ddecs2013b,
      title = {On Performance Estimation of a Scalable VLIW Soft-Core in XILINX FPGAs},
      booktitle = {Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)},
      pages = {181-186},
      year = {2013},
      month = {April},
      yy = {2013},
      mm = {4},
      author = {P. Pfeifer and Z.Pliva and M. Scholzel and T. Koal and H.T. Vierhaus} }
  • O. Hnilicka, "FPGA Architecture for Fast Floating Point Matrix Inversion Using Uni-dimensional Systolic Array Based Structure," in Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp. 267-270, 2013.

2012

International Journals

  • P. Reviriego, S. Pontarelli, J. Maestro and M. Ottavi, "Low-cost single error correction multiple adjacent error correction codes," in IET Electronics Letters, Vol. 48, No. 23, pp. 1470-1472, 2012. doi
  • P. Reviriego, S. Pontarelli, C. Bleakley and J. Maestro, "Area efficient concurrent error detection and correction for parallel filters," in IET Electronics Letters, Vol. 48, No. 20, pp. 1258-1260, 2012. doi

International Proceedings

  • A. Calimera, W. Liu, E. Macii, A. Nannarelli and M. Poncino, "Power and Aging Characterization of Digital FIR Filters Architectures," in Proc. 1st MEDIAN Workshop, pp. 1-6, 2012.
  • G. Theodorou, M. A. Skitsas, S. Chatzopoulos, C. A. Nicopoulos, N. Kranitis, M. K. Michael, A. Paschalis and D. Gizopoulos, "On-Line Software-Based Self-Test for Data TLBs," in Proc. 1st MEDIAN Workshop, pp. 65-70, 2012. bibtex
    @inproceedings {tc+2012,
      mm = {6},
      month = {June},
      yy = {2012},
      year = {2012},
      pages = {65-70},
      booktitle = {Proc. 1st MEDIAN Workshop},
      title = {On-Line Software-Based Self-Test for Data TLBs},
      author = {G. Theodorou and S. Chatzopoulos and N. Kranitis and A. Paschalis and D. Gizopoulos} }
  • S. Campagna and M. Violante, "On the Evaluation of the Performance Overhead of a Commercial Embedded Hypervisor," in Proc. 1st MEDIAN Workshop, pp. 59-63, 2012. bibtex
    @inproceedings {cv2012,
      mm = {6},
      month = {June},
      yy = {2012},
      year = {2012},
      pages = {59-63},
      booktitle = {Proc. 1st MEDIAN Workshop},
      title = {On the Evaluation of the Performance Overhead of a Commercial Embedded Hypervisor},
      author = {S. Campagna and M. Violante} }
  • M. Simkova and J. Kastil, "Verification of Fault-tolerant Methodologies for FPGA systems," in Proc. 1st MEDIAN Workshop, pp. 55-58, 2012. bibtex
    @inproceedings {sk2012,
      mm = {6},
      month = {June},
      yy = {2012},
      year = {2012},
      pages = {55-58},
      booktitle = {Proc. 1st MEDIAN Workshop},
      title = {Verification of Fault-tolerant Methodologies for FPGA systems},
      author = {M. Simkova and J. Kastil} }
  • V. S. Veeravalli and A. Steininger, "Monitoring Single Event Transient Effects in Dynamic Mode," in Proc. 1st MEDIAN Workshop, pp. 51-54, 2012. bibtex
    @inproceedings {vs2012,
      mm = {6},
      month = {June},
      yy = {2012},
      year = {2012},
      pages = {51-54},
      booktitle = {Proc. 1st MEDIAN Workshop},
      title = {Monitoring Single Event Transient Effects in Dynamic Mode},
      author = {V. S. Veeravalli and A. Steininger} }
  • J. Kastil, M. Straka and Z. Kotasek, "Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration," in Proc. 1st MEDIAN Workshop, pp. 47-50, 2012. bibtex
    @inproceedings {ksk2012,
      mm = {6},
      month = {June},
      yy = {2012},
      year = {2012},
      pages = {47-50},
      booktitle = {Proc. 1st MEDIAN Workshop},
      title = {Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration},
      author = {J. Kastil and M. Straka and Z. Kotasek} }
  • I. Akturk and O. Ozturk, "Reliability-Aware 3D Chip Multiprocessor Design," in Proc. 1st MEDIAN Workshop, pp. 45-46, 2012. bibtex
    @inproceedings {ao2012,
      mm = {6},
      month = {June},
      yy = {2012},
      year = {2012},
      pages = {45-46},
      booktitle = {Proc. 1st MEDIAN Workshop},
      title = {Reliability-Aware 3D Chip Multiprocessor Design},
      author = {I. Akturk and O. Ozturk} }
  • L. Guang, S. Jafri, B. Yang, J. Plosila and H. Tenhunen, "Embedding Fault-Tolerance with Dual-Level Agents in Many-Core Systems," in Proc. 1st MEDIAN Workshop, pp. 41-44, 2012. bibtex
    @inproceedings {gj+2012,
      mm = {6},
      month = {June},
      yy = {2012},
      year = {2012},
      pages = {41-44},
      booktitle = {Proc. 1st MEDIAN Workshop},
      title = {Embedding Fault-Tolerance with Dual-Level Agents in Many-Core Systems},
      author = {L. Guang and S. Jafri and B. Yang and J. Plosila and H. Tenhunen} }
  • M. Rozkovec, J. Jenicek and Z. Pliva, "Using deterministic test vectors to test FPGA circuit," in Proc. 1st MEDIAN Workshop, pp. 37-40, 2012.
  • P. Reviriego, C. Bleakley and J. A. Maestro, "Low Complexity Concurrent Error Detection for Complex Multiplication," in Proc. 1st MEDIAN Workshop, pp. 33-36, 2012. bibtex
    @inproceedings {rbm2012,
      mm = {6},
      month = {June},
      yy = {2012},
      year = {2012},
      pages = {33-36},
      booktitle = {Proc. 1st MEDIAN Workshop},
      title = {Low Complexity Concurrent Error Detection for Complex Multiplication},
      author = {P. Reviriego and C. Bleakley and J. A. Maestro} }
  • L. Chen and M. B. Tahoori, "Soft Error Propagation and Correlation Estimation in Combinational Network," in Proc. 1st MEDIAN Workshop, pp. 29-32, 2012. bibtex
    @inproceedings {ct2012,
      mm = {6},
      month = {June},
      yy = {2012},
      year = {2012},
      pages = {29-32},
      booktitle = {Proc. 1st MEDIAN Workshop},
      title = {Soft Error Propagation and Correlation Estimation in Combinational Network},
      author = {L. Chen and M. B. Tahoori} }
  • P. Rech, C. Aguiar, C. Frost and a. L. Carro, "Neutron-Induced Multiple Output Errors: a Reality on GPUs," in Proc. 1st MEDIAN Workshop, pp. 23-28, 2012. bibtex
    @inproceedings {ra+2012,
      mm = {6},
      month = {June},
      yy = {2012},
      year = {2012},
      pages = {23-28},
      booktitle = {Proc. 1st MEDIAN Workshop},
      title = {Neutron-Induced Multiple Output Errors: a Reality on GPUs},
      author = {P. Rech and C. Aguiar and C. Frost and and L. Carro} }
  • C. Bolchini, M. Carminati and A. Miele, "Towards the Design of Tunable Dependable Systems," in Proc. 1st MEDIAN Workshop, pp. 17-21, 2012. bibtex
    @inproceedings {bcm2012,
      mm = {6},
      month = {June},
      yy = {2012},
      year = {2012},
      pages = {17-21},
      booktitle = {Proc. 1st MEDIAN Workshop},
      title = {Towards the Design of Tunable Dependable Systems},
      author = {C. Bolchini and M. Carminati and A. Miele} }
  • G. Prenat, C. Bolchini, B. Dieny, M. Carminati, G. D. Pendina, A. Miele and K. Torki, "Hybrid CMOS/Magnetic Process Design Kit and application to the design of reliable and low-power non-volatile logic circuits," in Proc. 1st MEDIAN Workshop, pp. 13-16, 2012. bibtex
    @inproceedings {pd+2012,
      mm = {6},
      month = {June},
      yy = {2012},
      year = {2012},
      pages = {13-16},
      booktitle = {Proc. 1st MEDIAN Workshop},
      title = {Hybrid CMOS/Magnetic Process Design Kit and application to the design of reliable and low-power non-volatile logic circuits},
      author = {G. Prenat and B. Dieny and G. Di Pendina and K. Torki} }
  • S. Khan and S. Hamdioui, "Analyzing Combined Impacts of Parameter Variations and BTI in Nano-scale Logical Gates," in Proc. 1st MEDIAN Workshop, pp. 7-11, 2012.
  • M. A. Skitsas, C. A. Nicopoulos and M. K. Michael, "Toward Selective Software-Based Self-Testing in Multi-Core Microprocessors," in Proc. 1st MEDIAN Workshop, pp. 71-75, 2012. bibtex
    @inproceedings {snm2012,
      mm = {6},
      month = {June},
      yy = {2012},
      year = {2012},
      pages = {71-75},
      booktitle = {Proc. 1st MEDIAN Workshop},
      title = {Toward Selective Software-Based Self-Testing in Multi-Core Microprocessors},
      author = {M. A. Skitsas and C. A. Nicopoulos and M. K. Michael} }

Note: When publishing a paper that is an outcome of an activity fostered by MEDIAN, please acknowledge it in the paper, by adding a sentence such as the following ones:
  • This work was partially supported by EU COST Action IC1103 – MEDIAN – ManufacturablE and Dependable multIcore Architectures at Nanoscale
  • This is a joint collaboration in the framework of EU COST Action IC1103 – MEDIAN – ManufacturablE and Dependable multIcore Architectures at Nanoscale