The First Workshop on Manufacturable and Dependable
Multicore Architectures at Nanoscale (MEDIAN'12)
Annecy, France, June 1st, 2012
Advanced Program
| Time | Event | Description | |
|---|---|---|---|
| 08:00-08:30 | Registration | ||
| 08:30-08:45 | Opening Remarks | ||
| 08:45-09:15 | Keynote Talk by Magdy S. Abadir Achieving Reliable Zero-Defect Quality in an Unreliable World – Challenges and Potential Solutions |
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| 09:15 - 10:15 | 09:15-09:35 | O1.1 | A. Calimera, W. Liu, E. Macii, A. Nannarelli and M. Poncino Power and Aging Characterization of Digital FIR Filters Architectures |
| 09:35-09:55 | O1.2 | S. Khan and S. Hamdioui Analyzing Combined Impacts of Parameter Variations and BTI in Nano-scale Logical Gates |
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| 09:55-10:15 | O1.3 | P. Guillaume, D. Bernard, G. Di Pendina and T. Kholdoun Hybrid CMOS/Magnetic Process Design Kit and application to the design of reliable and low-power non-volatile logic circuits |
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| 10:15-10:30 | Coffee Break | ||
| 10:30 - 11:50 | 10:30-10:50 | O2.1 | C. Bolchini, M. Carminati and A. Miele Towards the Design of Tunable Dependable Systems |
| 10:50-11:10 | O2.2 | P. Rech, C. Aguiar, C. Frost and L. Carro Neutrons-Induced Multiple Output Errors: a Reality on GPUs |
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| 11:10-11:30 | O2.3 | L. Chen and M. Tahoori Soft Error Propagation and Correlation Estimation in Combinational Network |
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| 11:30-11:50 | O2.4 | P. Reviriego, C. Bleakely and J. A. Maestro Low Complexity Concurrent Error Detection for Complex Multiplication |
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| 12:00-14:00 | Lunch & Poster Session | ||
| 12:00 - 14:00 | P.1 | M. Rozkovec, J. Jeníček and Z. Plíva Using deterministic test vectors to test FPGA circuit |
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| P.2 | L. Guang, S. Asad, T. Yang, J. Plosila and H. Tenhunen Embedding Fault-Tolerance with Dual-Level Agents in Many-Core Systems |
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| P.3 | I. Akturk and O. Ozturk Reliability-Aware 3D Chip Multiprocessor Design |
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| P.4 | J. Kaštil, M. Straka and Z. Kotasek Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration |
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| P.5 | V. S. Veeravalli and A. Steininger Monitoring Single Event Transient Effects in Dynamic Mode |
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| P.6 | M. Šimková and J. Kaštil Verification of Fault-tolerant Methodologies for FPGA systems |
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| 14:00-14:30 | Invited Talk by Adrian Evans Case Study of SEU Effects in a Network Processor |
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| 14:30 - 15:30 | 14:30-14:50 | O3.1 | S. Campagna and M. Violante On the Evaluation of the Performance Overhead of a Commercial Embedded Hypervisor |
| 14:50-15:10 | O3.2 | G. Theodorou, N. Kranitis, A. Paschalis and D. Gizopoulos On-Line Software-Based Self-Test for Data TLBs |
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| 15:10-15:30 | O3.3 | M. A. Skitsas, C. A. Nicopoulos and M. K. Michael Toward Selective Software-Based Self-Testing in Future Multi-Core Microprocessors |
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| 15:30-16:00 | Closing remarks | ||
Registration to the workshop available at: http://ets2012.imag.fr/ets/
General co-Chairs
- Marco Ottavi
University of Rome “Tor Vergata”
ITALY
E-mail: ottavi@ing.uniroma2.it - Massimo Violante
Politecnico di Torino
ITALY
E-mail: massimo.violante@polito.it
Program co-Chairs
- Said Hamidioui
Delft University of Technology
NETHERLANDS
E-mail: s.hamdioui@tudelft.nl - Hans Manhaeve
Ridgetop Europe
BELGIUM
E-mail: hans.manhaeve@qstar.be
Publicity Chair
- Antonio Miele
Politecnico di Milano
ITALY
E-mail: miele@elet.polimi.it