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COST Action IC1103

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MEDIAN 2013 Workshop: deadline extension

Mar 14th, 2013

The deadile for submission to the 2nd Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale has been extended to March 22, 2013.

New MEDIAN publication: “A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only”

Feb 21st, 2013

The paper “A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only” by Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, and Marco Ottavi has been published on the IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No.3, pp.479-483, March 2013 (doi).

Abstract
Error correction codes (ECCs) have been used for decades to protect memories from soft errors. Single error correction (SEC) codes that can correct 1-bit error per word are a common option for memory protection. In some cases, SEC codes are extended to also provide double error detection and are known as SEC-DED codes. As technology scales, soft errors on registers also became a concern and, therefore, SEC codes are used to protect registers. The use of an ECC impacts the circuit design in terms of both delay and area. Traditional SEC or SEC-DED codes developed for memories have focused on minimizing the number of redundant bits added by the code. This is important in a memory as those bits are added to each word in the memory. However, for registers used in circuits, minimizing the delay or area introduced by the ECC can be more important. In this paper, a method to construct low delay SEC or SEC-DED codes that correct errors only on the data bits is proposed. The method is evaluated for several data block sizes, showing that the new codes offer significant delay reductions when compared with traditional SEC or SEC-DED codes. The results for the area of the encoder and decoder also show substantial savings compared to existing codes.

The work is a collaboration within the MEDIAN Cost Action between the Universidad Antonio de Nebrija and the University of Rome Tor Vergata, Rome.

New MEDIAN publication: “Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability”

Feb 21st, 2013

The paper “Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability” by Marcela Simkova, Zdenek Kotasek and Cristiana Bolchini will be presented at the IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems as a poster.

The paper is a joint work carried out during a MEDIAN Short Term Scientific Mission, between Brno University of Technology and Politecnico di Milano.

Core group meeting in Rome

Feb 21st, 2013

The meeting will wrap up the first year activities of the MEDIAN Cost Action. It will be held at

CNR  (Research National Council),
piazzale Aldo Moro 7, Rome
near the University of Rome “La Sapienza”
[map]

Program of the day

9:25 Welcome from the organizers

9:30 -10:30 Session I – Presentation of Working groups activities (15 min +5 Q&A)

WG1 Mehdi Tahoori, Lorena Anghel

WG2 Cristiana Bolchini, Salvatore Pontarelli

WG3 Dimitris Gizopoulos, Maria Michael

10:30 11:00 Coffee break

11:00 12:00 Session II – Presentation of Working groups activities

WG4: Antonis Paschalis, Pedro Reviriego

WG5 Oliver Bringmann, Viacheslav Izosimov

WG6 Hans Manhaeve, Christos Strydis

12:00 12:30 Presentation of the complete report and planning of D&T contribution

12:30 14:00 Lunch

14:00 15:30 Organizing committee meeting for Training School in Rome

15:30 16:00 Coffee break

16:00 17:00 Possible extra session on Training School.  Wrap up.

WG1 Focus meeting in Rome

Feb 21st, 2013

Program

9:25 Opening and greeting from the organizers

9:30 -10:30 Invited talk Ben Kaczer Principal Scientist at IMEC. Title of talk: “Reliability Aware Design:  From Single Defect Physics to Circuit Simulations”

10:30 – 10:50 Coffee break

10:50 – 12:30 Session I (10 minutes per talk + 5 minutes Q&A)

  1. Universidad Antonio de Nebrija, Madrid, Spain, J.A. Maestro and P. Reviriego
  2. University of Turku, Finland, Kameswar Rao Vaddina
  3. Semcon AB, Sweden,  Viacheslav Izosimov
  4. Technical University of Denmark, A. Nannarelli and P. Pop
  5. Tallinn University of Technology, ESTONIA, Maksim Jenihhin
  6. iRoc Technologies, France, Enrico Costenaro
  7. University of Rome Tor Vergata, Stefano Campitelli

12:30 14:00 Lunch

14:00 14:45 Session II (10 minutes per talk + 5 minutes Q&A)

  1.  TOBB University of Economics and Technology, Turkey, Oguz Ergin
  2. Karlsruhe Institute of Technology, Karlsruhe, Germany, Mehdi Tahoori
  3. Delft University of Technology (TUDelft) Said Hamdioui

14:45 Summary from the organizers and explanation of possible networking instruments

15:00 16:00 Breakout sessions I

 16:00 16:30 Coffee break

16:30 17:45 Breakout sessions II

17:45 18:15 Summary of breakout discussions

18:15 Conclusions from the organizers

MC Meeting and WG Meetings in Berlin 20/1/2013

Jan 12th, 2013
The Management Committee Meeting and the working group meetings will be held on January 20th, 2013 in Berlin, in conjunction with the HiPEAC conference.

  • Venue: Radissonblu hotel Berlin (http://www.radissonblu.com/hotel-berlin)
  • Schedule:
    Time Description
    09:30-10:30 MC meeting (part 1)
    10:30-11:00 morning coffee break
    11:00-12:30 MC meeting (part 2)
    12:30-14:00 lunch
    14:00-16:00 Working group meetings part 1
    16:00-16:30 coffee break
    16:30-18:00 Working group meetings part 2

     

  • Agenda

Call for STSM Applications – Additional Round before Feb. 28, 2013

Dec 19th, 2012

There are still open opportunities for STSMs, to be completed before February 28, 2013.
The results of the evaluations will be notified to the applicants within a week after submission.

CALL for Conference Grant for Early Stage Researchers – deadline Jan. 31, 2013

Dec 19th, 2012

11th Call Now Open – deadline: 31 January 2013

The ICT Domain offers 3 supporting grants (max. 3000 Euro each) per year for Early Stage Researchers to participate in an international conference outside of COST Action activities (COST Strategy for Early Stage Researchers, COST 212/07).

The tenth call for applications is now open. To apply, please use the attached documents:

  • Call for Conference Grants (PDF format) – Deadline: 31 January 2013
  • Application form (MS Word format – to be returned in the same format)
  • Conference Grant Overview and Check-list (MS Excel format – to be filled in and returned)

New MEDIAN publication: “Low-cost single error correction multiple adjacent error correction codes”

Nov 8th, 2012

The paper “Low-cost single error correction multiple adjacent error correction codes” by Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, and Marco Ottavi has been published on the IET ELECTRONICS LETTERS, Vol. 48 No. 23, pp.479-483, November 2012 (doi).

Abstract
Soft errors that affect flip-flops are a major issue in advanced electronic circuits. As technology scales, multiple bit errors become more likely. This limits the applicability of traditional protection techniques like triplication with voting or single error correction codes that can correct only one error. Multiple errors tend to affect adjacent bits, and therefore it is interesting to use error correction codes that can correct adjacent errors. The issue with these codes is that they require a large area and delay that limits their use to protect flip-flops in circuits. Presented are codes that can be implemented with low area and delay and can correct multiple adjacent errors.

The work is a collaboration within the MEDIAN Cost Action between the Universidad Antonio de Nebrija and the University of Rome Tor Vergata, Rome.

New MEDIAN publication: “Area efficient concurrent error detection and correction for parallel filters”

Sep 27th, 2012

The paper “Area efficient concurrent error detection and correction for parallel filters ” by Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, and Marco Ottavi has been published on the IET ELECTRONICS LETTERS, Vol. 48 No. 20, pp.1258-1260, September 2012 (doi).

Abstract
Soft errors that affect flip-flops are a major issue in advanced electronic circuits. As technology scales, multiple bit errors become more likely. This limits the applicability of traditional protection techniques like triplication with voting or single error correction codes that can correct only one error. Multiple errors tend to affect adjacent bits, and therefore it is interesting to use error correction codes that can correct adjacent errors. The issue with these codes is that they require a large area and delay that limits their use to protect flip-flops in circuits. Presented are codes that can be implemented with low area and delay and can correct multiple adjacent errors.

The work is a collaboration within the MEDIAN Cost Action between the Universidad Antonio de Nebrija and the University of Rome Tor Vergata, Rome.